HW-V5-ML555-G【PDF 52/108 页】BOARD EVAL FOR VIRTEX-5 ML555

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Chapter 3: Hardware Description

R

be configured as a serial COM port for the user to continue working with serial

communication utilities like HyperTerminal or Tera Term Pro.

The CP210x USB-to-UART Bridge VCP drivers can be downloaded from the Silicon

Laboratories website at:

http://www.silabs.com/tgwWebApp/public/web_content/products /

Microcontrollers/en/MCU_Downloads.htm

For technical information and support for the CP210x USB-to-UART bridge controller

integrated circuit and the associated VCP device driver, visit the Silicon Laboratories

website at www.silabs.com .

The ML555 FPGA must have a UART design instantiated to communicate with the PC on

the USB interface. A reference design and/or bit image is included on the CD ROM to

permit testing the FPGA to VCP interface. The reference design utilizes the MicroBlaze soft

processor and a UART core to communicate to the PC terminal window.

The ML555 board provides a USB Type-B device port connector that is intended to be

cabled to the host computer with a USB Type-A port connector.

Table 3-17 describes the USB interface pin assignments.

Table 3-17:

USB

USB Connector Signal Names and Pin Assignments

Connector

(J1) Pin

1

2

3

4

Signal Name

VBUS

USB_DATA_N

USB_DATA_P

GROUND

Description

+5V from HOST system (not used)

Bidirectional differential serial data (n-side)

Bidirectional differential serial data (p-side)

Signal ground

Clock Generation

The clock generation section of the ML555 board provides three fixed, two programmable,

and two pairs of differential SMA inputs for clock sources:

1.

2.

3.

Epson EG-2121CA-125.0000M-LHPAB 2.5V LVDS (differential) oscillator

125 MHz FPGA oscillator for Gigabit Ethernet

Epson SG-8002CA-30.0000M-PCC 3.3V LVCMOS (single-ended) oscillator

This clock is buffered via U9. It goes to the CPLD and one of the FPGA global clock

inputs.

Epson EG-2121CA-200.0000M-PHPAB 2.5V LVPECL (differential) oscillator

One pair of SMA clock inputs is connected to the global clock bank, and the other pair of

SMA clock inputs is connected to the GTP_DUAL tile X0Y3 MGTREFCLK inputs. The

global clock SMA ports can also be used as an output port to route internal debug signals

for triggering or viewing on an oscilloscope. Consult the Virtex-5 FPGA User Guide for

additional information on clocking and the appropriate I/O standards for high-speed

clock and data signals.

52

Virtex-5 FPGA ML555 Development Kit

UG201 (v1.4) March 10, 2008

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